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fedr37v12841a-002-02 issue date: oct. 01, 2008 mr37v12841a 128m 1?bit serial production programmed rom (p2rom) 1/15 general description the mr37v12841a is a 128mbit production programmed read-only memory, which is configured as 134,217,728word 1-bit. the mr37v12841a supports a simple read operation using a single 3.3v power supply and a serial peripheral interfa ce (spi) compatible serial bus. the mr37v12841a have data programmed and have functions tested at oki semiconductor factory. (using the dc pins for the programming function is not allowed ) features read operation - +3.3 v power supply - 134,217,728 1-bit - access time: 33mhz serial clock (fast-read) - 20mhz serial clock (read) - read identification instruction - active read current: 30ma(fast-read) - 20ma(read) - standby current : 50 a - serial clock input and data input/output - input data format : 1-byte command code, 3-byte address, 1-byte dummy (fast-read) 1-byte command code, 3-byte address (read) packages MR37V12841A-XXXMP - 16-pin plastic sop (p-sop16-375-1.27-k) pin descriptions pin name functions under read operation #cs chip select si serial data input so serial data output sclk clock input v cc power supply voltage gnd ground dc don?t care ( 0v - vcc ) program power supply voltage vpp under programming operation nc non connection
fedr37v12841a-002-02 mr37v12841a / p2rom 2/15 read command definition command read array (byte) note 1 st 03[h] 1 2 nd ad1 2 3 rd ad2 2 4 th ad3 2 action n byte read out until #cs goes high 3 note: 1. the 1 st command 03[h] is a read command 2. ad1 to ad3 are address input data 3. data output details of command and address are shown as follows. 1-byte command code read 0 0 0 0 0 0 1 1 3-byte address ad1: a23 a22 a21 a20 a19 a18 a17 a16 ad2: a15 a14 a13 a12 a11 a10 a9 a8 ad3: a7 a6 a5 a4 a3 a2 a1 a0
fedr37v12841a-002-02 mr37v12841a / p2rom 3/15 fast read command definition command read array (byte) note 1 st 0b[h] 1 2 nd ad1 2 3 rd ad2 2 4 th ad3 2 5 th x 3 action n byte read out until #cs goes high 4 note: 1. the 1 st command 0b[h] is a read command 2. ad1 to ad3 are address input data 3. x is a dummy cycle 4. data output details of command and address are shown as follows. 1-byte command code fast-read 0 0 0 0 1 0 1 1 3-byte address ad1: a23 a22 a21 a20 a19 a18 a17 a16 ad2: a15 a14 a13 a12 a11 a10 a9 a8 ad3: a7 a6 a5 a4 a3 a2 a1 a0
fedr37v12841a-002-02 mr37v12841a / p2rom 4/15 read identification command definition command read array (byte) note 1 st 9f[h] 1 action 3 byte read out 2 note: 1. the 1 st command 9f[h] is a read identification command 2. identification output details of command and address are shown as follows. 1-byte command code rdid 1 0 0 1 1 1 1 1 identification definition device identification manufacturer identification type capacity ae[h] 41[h] 16[h]
fedr37v12841a-002-02 mr37v12841a / p2rom 5/15 device operation 1. command ?03h? or ?0bh? makes this lsi become and keep active mode until next #cs high. 2. incorrect command makes this lsi become and keep standby mode until next #cs low. in standby mode, so pin is high-z. command description 1. read array this command consists of the 4-byte code. the 1 st code is a command which decides if the device becomes standby or active mode. the 1 st code ?03h? activates the device. the 2 nd code to the 4 th code are address inputs. 2. fast read array this command consists of the 5-byte code. the 1 st code is a command which decides if the device becomes standby or active mode. the 1 st code ?0bh?activates the device. the 2 nd code to the 4 th code are address. the 5 th code is a dummy cycle. 3. identification read array this command consists of the 1-byte code. the 1 st code is a command which decides if the device becomes standby or active mode. the 1 st code ?9fh?activates the device. 4. standby when #cs is high, the device is put in standby mode at the next rising edge of sclk. maximum standby current is 10ua. when the above-mentioned 1 st code is incorrect command, the device is put in standby mode at the next rising edge of sclk. data sequence the data is serially sent out through so pin, synchronized w ith the falling edge of sclk. meanwhile input data is also serially read in through si pin, synchronized with the rising edge of sclk. the bit sequence for both input and output data are bit7 (msb) first, bit6, bit 5, ?, and bit0(lsb). address sequence the address assignment is described at the command definition on page 2, 3.
fedr37v12841a-002-02 mr37v12841a / p2rom 6/15 absolute maximum ratings parameter symbol condition value unit storage temperature tstg ? ?55 to 125 c input voltage v i ?0.5 to v cc +0.5 v output voltage v o ?0.5 to v cc +0.5 v power supply voltage v cc relative to v ss ?0.5 to 5 v power dissipation per package p d ta = 25c 1.0 w output short circuit current i os ? 10 ma recommended operating conditions parameter symbol conditio n min. typ. max. unit operating temperature under bias ta 0 ? 70 c v cc power supply voltage v cc 3.0 ? 3.6 v input ?h? level v ih 2.4 ? v cc +0.5 ? v input ?l? level v il v cc = 3.0 to 3.6 v ?0.5 ?? ? 0.6 v voltage is relative to v ss . ? : vcc+1.5v(max.) when pulse width of positive overshoot is less than 10ns. ?? : -1.5v(min.) when pulse width of ne gative overshoot is less than 10ns. pin capacitance (v cc = 3.3 v, ta = 25c, f = 1 mhz) parameter symbol conditio n min. typ. max. unit input c in1 v i = 0 v ? ? 8 output c out v o = 0 v ? ? 10 dc c dc v i = 0 v ? ? 200 pf
fedr37v12841a-002-02 mr37v12841a / p2rom 7/15 electrical characteristics dc characteristics (v cc = 3.0v-3.6v, ta = 0 to 70c) parameter symbol conditio n min. typ. max. unit input leakage current i li v i = 0 to v cc ? ? 10 a output leakage current i lo v o = 0 to v cc ? ? 10 a i sb1 #cs = v cc ? ? 50 a v cc power supply current (standby) i sb2 #cs = v ih ? ? 1 ma v cc power supply current (read) i cc1 #cs = v il ,f = 20mhz so= open ? ? 20 ma v cc power supply current (fast read) i cc1 f #cs = v il ,f = 33hz so= open ? ? 30 ma input ?h? level v ih ? 2.4 ? v cc +0.5 ? v input ?l? level v il ? ?0.5 ?? ? 0.6 v output ?h? level v oh i oh = ?100 a vcc-0.2 ? ? v output ?l? level v ol i ol = 500 a ? ? 0.4 v voltage is relative to v ss . ? : vcc+1.5v(max.) when pulse width of positive overshoot is less than 10ns. ?? : -1.5v(min.) when pulse width of ne gative overshoot is less than 10ns.
fedr37v12841a-002-02 mr37v12841a / p2rom 8/15 ac characteristics ( tsclk=33mhz, v cc = 3.0v-3.6v, ta = 0 to 70c) parameter symbol condit ion min. max. unit clock frequency t sclk ? ? 33 * mhz clock high time t skh ? 11 ? ns clock low time t skl ? 11 ? ns clock rise time t r ? ? 4 ns clock fall time t f ? ? 4 ns #cs lead clock time t csa ? 5 ? ns #cs setup time t cs ? 5 ? ns #cs lag clock time t csb ? 5 ? ns #cs hold time t ch ? 5 ? ns #cs high time t csh ? 100 ? ns si setup time t ds ? 2 ? ns si hold time t dh ? 10 ? ns access time t aa ? ? 8 ns so hold time t doh ? 0 ? ns so floating time t doz ? ? 8 ns ( tsclk=20mhz v cc = 3.0v-3.6v, ta = 0 to 70c) parameter symbol condition min. max. unit clock frequency t sclk ? ? 20 ** mhz clock high time t skh ? 20 ? ns clock low time t skl ? 20 ? ns clock rise time t r ? ? 5 ns clock fall time t f ? ? 5 ns #cs lead clock time t csa ? 10 ? ns #cs setup time t cs ? 10 ? ns #cs lag clock time t csb ? 5 ? ns #cs hold time t ch ? 5 ? ns #cs high time t csh ? 100 ? ns si setup time t ds ? 5 ? ns si hold time t dh ? 10 ? ns access time t aa ? ? 15 ns so hold time t doh ? 0 ? ns so floating time t doz ? ? 10 ns *: fast-read instructions **: read instructions measurement conditions output load input signal level vcc/0v input timing reference level 2.4v/ 0.6v output load 30 pf output timing reference level 0.5 vcc output 30 pf (including scope and jig)
fedr37v12841a-002-02 mr37v12841a / p2rom 9/15 timing chart (read cycle) incorrect command makes this lsi become and keep standby mode until next #cs rising edge. in standby mode, so pin is high-z. si bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 si sclk #cs so hi - z 1 st byte = incorrect code standby standby t doz t skh t skl t csa t r t f serial data input/output timing #cs so bit 7 bit 6 bit 0 bit 7 bit 0 t cyc t ds t dh t aa t doh standby timing bit 6 sclk si t csb t csh t cs t ch
fedr37v12841a-002-02 mr37v12841a / p2rom 10/15 note: 1. input data are latched at sclk-rising edge. 2. data-output starts at sclk-falling edge in bit0 of the 4 th byte. read array timing waveform si bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 si sclk #cs so bit 3 bit 2 bit 1 bit 0 bit 7 hi - z (n-1) th data output n th data output (n+1) th data output si bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 si sclk #cs so hi - z 1 st data output bit 1 bit 0 bit 7 bit 6 bit 5 4 th byte ad3 1 st data output 2 nd data output don?t care *note2 si bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 si sclk #cs so hi - z 1 st byte command bit 7 bit 6 bit 5 bit 4 2 nd byte ad1 bit 3 *note1
fedr37v12841a-002-02 mr37v12841a / p2rom 11/15 note: 1. input data are latched at sclk-rising edge. 2. data-output starts at sclk-falling edge in bit0 of the 5 th byte. si bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 si sclk #cs so bit 3 bit 2 bit 1 bit 0 bit 7 hi - z (n-1) th data output n th data output (n+1) th data output si bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 si sclk #cs so hi - z 1 st data output bit 1 bit 0 bit 7 bit 6 bit 5 5 th byte dummy 1 st data output 2 nd data output don?t care *note2 si bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 si sclk #cs so hi - z 1 st byte command bit 7 bit 6 bit 5 bit 4 2 nd byte ad1 bit 3 *note1 fast read array timing waveform
fedr37v12841a-002-02 mr37v12841a / p2rom 12/15 note: 1. input data are latched at sclk-rising edge. 2. data-output starts at sclk-falling edge in bit0 of the 1 st byte. read identification timing waveform si bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 si sclk #cs so hi - z 1 st byte command bit 7 bit 6 bit 5 bit 4 bit 3 manufacturer identification *note1 don?t care *note2 si bit 1 bit 0 bit 2 si sclk #cs so device identification bit 1 bit 0 bit15 bit14 bit13 don?t care hi - z t csb
fedr37v12841a-002-02 mr37v12841a / p2rom 13/15 package dimensions notes for mounting the surface mount type package the surface mount type packages are very susceptible to h eat in reflow mounting and hum idity absorbed in storage. therefore, before you perform reflow mounting, contact oki semiconductor?s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (unit: mm)
fedr37v12841a-002-02 mr37v12841a / p2rom 14/15 revision history page document no. date previous edition current edition description fedr37v12841a-02-01 nov. 9, 2006 ? ? final edition 1 fedr37v12841a-02-02 mar. 16, 2007 13 13 replaced package diagram fedr37v12841a-002-02 oct. 1, 2008 ? ? changed company logo and name to oki semiconductor
fedr37v12841a-002-02 mr37v12841a / p2rom 15/15 notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki semiconductor assumes no responsibility or liabilit y whatsoever for any failure or unusual or unexpected operation resulting from misuse , neglect, improper installati on, repair, alteration or accide nt, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party?s indust rial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the inform ation and drawings contained herein. no responsibility is assumed by us for any infringement of a third party?s right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not, unless specifically author ized by oki semiconductor authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffi c and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining th e legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 2008 oki semiconductor co., ltd.

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